TL;DR — Nvidia controls roughly 60% of TSMC’s advanced chip packaging capacity, the process that turns GPU dies into finished AI accelerators. That number predicts Nvidia’s 2026 output better than anything said on an earnings call.
Every quarter, half a dozen hyperscaler executives get on a call and describe next year’s AI roadmap in adjectives. TSMC just described one in wafers, and it’s a better predictor than any of the keynotes. Nvidia holds roughly 60% of TSMC’s advanced packaging capacity for 2026. Add Broadcom and AMD, and the top three customers account for more than 85% of it. Whatever anyone else says about their compute plans for next year, that allocation sheet is the real ceiling, because a keynote slide doesn’t require eighteen months of fab lead time — and slides don’t sell out.
The Bottleneck Moved From the Chip to the Box It Ships In
An AI accelerator isn’t just a fabricated die. It’s a compute chip bonded to stacks of high-bandwidth memory through a process called CoWoS — chip-on-wafer-on-substrate — and until that bonding happens, what TSMC produced is expensive silicon, not a product Nvidia or anyone else can ship. For the past two years, the industry’s constraint has quietly shifted from raw wafer fabrication to that packaging step. CoWoS capacity, along with TSMC’s leading-edge N3 node, is sold out through the end of 2026, with lead times now stretching into 2027. Total CoWoS demand is set to hit roughly one million wafers in 2026, up from about 370,000 in 2024 — a near-tripling in two years that the industry’s packaging lines still haven’t fully caught up to.
Who Actually Gets the Capacity
Nvidia’s 60% share of that capacity isn’t a market-share statistic pulled from a research note — it’s an allocation decision TSMC has already made, locking in who gets to actually ship AI silicon over the next several quarters regardless of how the demand story develops elsewhere. Broadcom and AMD split most of what’s left among the top three. Everyone else — every AI chip startup, every hyperscaler’s custom silicon program, every company promising an accelerated 2027 roadmap — is negotiating for capacity that’s already spoken for. If you want to know whose AI ambitions are backed by actual production slots and whose are backed by a press release, the allocation queue is a more honest answer than the roadmap deck.
The Numbers Behind the Sold-Out Sign
TSMC’s own results explain why it can afford to let the queue run this long. Second-quarter 2026 revenue came in at $39.6 billion to $40.2 billion depending on the reporting currency conversion, a record, up 36% year over year and at the high end of the company’s own guidance. Gross margin held at 67.7%. Nodes at 7 nanometers and below — the leading-edge processes that AI compute actually runs on — made up 77% of wafer revenue, which tells you how concentrated TSMC’s growth already is in exactly the capacity that’s sold out.
Management didn’t just report a strong quarter, it raised the forecast for the year: full-year 2026 revenue growth is now guided to slightly above 40%, up from a prior guide of over 30%. Capital expenditure guidance rose alongside it, to $60 billion–$64 billion for the year from a prior $52 billion–$56 billion, and TSMC layered on an additional $100 billion of investment in Arizona, pushing its cumulative planned commitment there toward $265 billion. That’s not a company hedging against a demand air pocket. That’s a company betting its balance sheet that the sold-out sign stays up for years, not quarters.
What This Sets as the Real Ceiling
We’ve spent this earnings season tracking the demand side of the AI buildout — the hyperscaler commitments piling up on Microsoft’s backlog, the capital trade-offs showing up in Alphabet’s decision to zero out its buyback in favor of infrastructure spending. TSMC’s allocation sheet is the other half of that story: the supply-side ceiling that determines how much of that demand actually turns into shipped compute, on what timeline, and for whose products first. A hyperscaler can commit to any capex number it wants. What TSMC’s packaging lines can physically produce, and who’s first in line for it, is a separate and arguably more binding constraint on how fast this cycle can actually move.
Sources: TSMC Q2 2026 earnings call transcript and investor materials, July 2026; industry reporting on CoWoS advanced packaging capacity and allocation. Third Pole Markets holds no position in TSMC, Nvidia, Broadcom, or AMD as of publication. This is not investment advice — see our About page for our full disclosure policy.
Packaging capacity details are discussed in TSMC’s investor relations disclosures and Nvidia’s investor relations page.
